1. Field of the Invention This invention relates to an improved process for removing residues remaining after etching a polysilicon layer on an integrated circuit structure. More particularly, the improvement comprises treating an integrated circuit structure, after a polysilicon etch, with an aqueous hydroxide/peroxide solution to selectively remove residues remaining after the anisotropic etching of the polysilicon layer.
2. Description of the Related Art During the construction of an integrated circuit structure, a polysilicon layer may be formed which covers a raised portion or step on the integrated circuit structure. Such a step might, for example, comprise an oxide portion such as an isolation oxide or an oxide-covered polysilicon line, e.g., a poly 1 layer. Subsequent masking and anisotropic etching of this polysilicon layer, for example, to form another polysilicon line, can result in undesirable residues being left behind on the sidewalls of the polysilicon lines on the integrated circuit structure after the anisotropic etching step.
FIG. 1 shows such a polysilicon layer formed on an integrated circuit substrate, while FIGS. 2 and 3 show the structure of FIG. 1 respectively after first and second stages of an anisotropic etch of polysilicon layer. In FIG. 1, polysilicon layer 20 is formed over silicon substrate 2 on which was previously formed a gate oxide layer 4 and raised steps 10 comprising polysilicon lines 12 covered by a oxide portion 14. A photoresist mask has been applied and patterned leaving photoresist portion 32 over a portion of polysilicon layer 20 where a line is to be formed from polysilicon layer 20. It will also be noted that a native oxide layer 16, of usually less than about 30 Angstroms thickness, is present over polysilicon layer 20.
Conventionally, polysilicon layer 20 is anisotropically etched (to avoid undercutting of the polysilicon beneath mask 32) by, for example, an RIE etch, using Cl.sub.2, HCl, and HBr gases to remove the exposed portions of polysilicon layer 20 down to the level of oxide portion 14 and gate oxide 4, as shown in FIG. 2, while observing the emission from the plasma with optical emission spectroscopy to monitor increases in the intensity of the Cl.sub.2 line indicative that the Cl.sub.2 is not being used to etch polysilicon. This first portion of the RIE etch process leaves polysilicon shoulders 22 and oxide portions 18, representing the inverted corners of oxide layer 16 over polysilicon layer 20 where polysilicon layer 20 begins to cross over each step 10, remaining on the sides of step 10 due to the greater thickness of polysilicon layer 20 at these points as shown in FIG. 2.
The structure is then subjected to a further RIE etch or overetch to remove the remaining portions of polysilicon layer 20 on the sides of step 10, as in FIG. 3, by changing the chemistry of the RIE etch to provide a higher concentration of O.sub.2 or HBr gas and a lower concentration of Cl.sub.2 gas, as well as a reduction in power density from, e.g., about 250-350 watts down to about 50-120 watts for a 4" wafer, to make the etch more selective in the etching of polysilicon, which will reduce or eliminate inadvertent etching of gate oxide layer 4.
However, as can be seen in FIG. 3, completion of the RIE etch leaves polymeric silicon and oxide-containing materials comprising sidewalls 26 on the sides of polysilicon line 28 and photoresist 32.
Conventionally, in the prior art, such residues of polymericsilicon/oxide-containing materials forming sidewalls 26 were removed by dipping the integrated circuit structure in HF. However, the HF will also etch the gate oxide and, therefore, unless the wet etch conditions are very carefully controlled, the gate oxide will also be removed, exposing the underlying silicon substrate.
It would, therefore, be desirable to provide an improved process for the selective removal of residues, and in particular, sidewalls residues left on raised polysilicon lines, after an anisotropic etching step, with minimum damage to oxide portions in or on the integrated circuit structure such as gate oxide over the silicon substrate, including elimination of undercutting of the remaining polysilicon portions.